1. Field of the Invention
The present invention relates to circuitry for protecting an integrated circuit against electrostatic discharge (ESD).
2. Discussion of the Prior Art
Electrostatic discharge (ESD) in semiconductor integrated circuits is a well-known problem. The inadvertent presence of a sudden voltage spike in an integrated circuit can cause physical destruction of circuit features. For example, ESD-induced spikes can rupture the thin gate oxides of field effect transistors.
The most common source of ESD stress is user handling of integrated circuit devices, particularly during testing. The human body can accumulate a static electric charge as high as 2000V, an amount of charge that can easily rupture gate oxide or other circuit features.
FIG. 1 shows an integrated circuit device having a number of input pads AoAn and a number of output pads BoBn. An example of an integrated circuit having this general architecture is a multi-channel transceiver.
A common ESD protection scheme for integrated circuits of the type shown in FIG. 1 is to simply insert diodes that clamp the input line of interest to supply (diodes D175, D176 and 177 in FIG. 1) and ground (Schottky diodes Q155, Q156, Q157 and Q167, Q168, Q169 and Q171 in FIG. 1). However, this scheme fails to protect the testing input while other inputs are grounded.
In some circuits, multiple grounds are employed, for example, in some multi-channel transceivers. Also, quite often a power output transistor which carries very high current requires separate ground return to avoid ground bouncing and overall device stability problems. Under these circumstances, the conventional shunt diode ESD scheme shown in FIG. 1 will not protect the device from this over-stressed transient voltage.